Lecture Two: Digital Design (Combination Circuit Design)

review of digital design

1) Combination  --> output is a direct function of inputs
  1. first ,draw a block diagram, indetfiy inputs & outputs
  2. second depending the size of the problem, use 1 kmap per output
  3. size of the k-map = to number of inputs, in terms of variables
   example:  4 inputs, 3 outputs
    - 3 k-maps
    - size of k-map  = 4 variable 4 k-map

Most of the problems can be easily solved if the number of inputs is small, but if the number of inputs is large it is much harder to design, combination circuit design is broken into 2 types of techniques


{ # of inputs <= 6 }                   { # of inputs > 6 }                                    

use the tehqniue above               A)  we can then use the "Heuristic Approach"
                                                    example: e.g.  "Priority encoder Design"

                                               





2) Sequential

Lecture One: Questions for Prof.

1. Will I need to know how to add binary numbers to be successful in this course?

2. There appears to be NO homework for lecture #1 is this true? You mentioned about completing one of the k-maps for the 2-bit adder example, but you didn't say that this should be turned in rather it was something we could just do on our own.

3. I have NO digital design or circuit design experience, I hope I can make it?

4. The good news is by the end of the 1st lecture, while I didn't know everything, it did start to make sense.

Lecture 1: Course Introduction, Digital Design Review

Contact Information 
Prof: Ausif Mahmood
eMail: mahmood@bridgeport.edu

Phone: 203-576-4737

Office: Tech Building Rm 225 (Rm 228)

website: http://kiwi.bridgeport.edu/CPE510

username: pwd:

GA: Mohamad Abuzneid

GA eMail: mohamad@bridgeport.edu

Grading

• Lectures & materials are all on the website.
• Phd students are grouped
• Masters students are grouped
• Assignments & Projects are KEY to getting a good grade.
• Prof: Mentioned about how students do copy each other, the test will really determine what you have really learned.

Textbook 

Computer Architecture A Quantitive Approace , 4th Edition

by.John L. Hennessy (Author), David A. Patterson (Author)

Authors are Inventors of Reduced Instruction Set Architecture - RISC

Welcome to the CPE510 Website

This is a screen shot of the Class website:

This is the Listing of Lectures:

CPE 510-Computer Architecture: Course Outline

CPE 510-Computer Architecture

This course covers the architecture of both single processor and multi-processor designs. The course starts out with the design of a complete 32/64-bit RISC type processor. After specifying the instruction set, the data path and control sequence for the processor are designed. The pipelining and removal of structural, data and control hazards is carried out. Other topics covered include floating point pipeline design super scalar design, multiprocessor architectures including systolic and data flow designs, interconnection networks for multiprocessors and routing design.

3 lectures hours, 3 semester hours.

Prerequisite: CPE 312 (under graduate computer organization course) or equivalent.

Textbook:

Computer Architecture: A quantitative approach – third edition

By David A. Patterson and John L. Hennessey, Morgan Kaufmann 2003.

Reference Book: same as above but second edition, Morgan Kaufmann 1996.

Coordinator: Ausif Mahmood, Professor, Computer Science and Engineering

Phone: 203-576-4737, Email: mahmood@bridgeport.edu