CPE 510-Computer Architecture: Course Outline

CPE 510-Computer Architecture

This course covers the architecture of both single processor and multi-processor designs. The course starts out with the design of a complete 32/64-bit RISC type processor. After specifying the instruction set, the data path and control sequence for the processor are designed. The pipelining and removal of structural, data and control hazards is carried out. Other topics covered include floating point pipeline design super scalar design, multiprocessor architectures including systolic and data flow designs, interconnection networks for multiprocessors and routing design.

3 lectures hours, 3 semester hours.

Prerequisite: CPE 312 (under graduate computer organization course) or equivalent.

Textbook:

Computer Architecture: A quantitative approach – third edition

By David A. Patterson and John L. Hennessey, Morgan Kaufmann 2003.

Reference Book: same as above but second edition, Morgan Kaufmann 1996.

Coordinator: Ausif Mahmood, Professor, Computer Science and Engineering

Phone: 203-576-4737, Email: mahmood@bridgeport.edu

TOPICS:

1. Review of Computer Architecture Concepts (5 hrs)

Design of a small 8-bit Processor, Instruction set and assembly language design, Datapath, Control Sequence design (3 hrs)

2. Design of a 32 bit RISC pipelined processor (3 hrs)

Fundamental ideas in a RISC architecture

Instruction set and assembly language design

Datapath, ALU design for the 32 bit processor

Control sequence design.

3. Design of pipelining for the RISC processor (9 hrs)

Hazards in pipelining, their detection and stalls.

Structural, data and control hazards, forwarding and

branch prediction schemes to reduce pipelining stalls,

Compiler Optimization techniques to reduce hazards.

4. Floating point instruction and pipelining issues (2 hours)

5. Mid term Test . (1.5 hrs)

6. Extending the pipelined design to 64 bits. (2 hours)

Instruction set, pipelining issues in the 64-bit design. (2 hours)

7. Superscalar design . (4 hrs)

Multiple issue of instructions, VLIW design.

8. Multiprocessor architectures (5 hrs)

SIMD, MIMD classifications, Dataflow architecture and

Systolic arrays.

9. Interconnection networks for multiprocessors (5 hrs)

Routing protocols and algorithm design for deadlock free routing.

10. Final Exam . (1.5 hrs)