Prof: Ausif Mahmood
eMail: mahmood@bridgeport.edu
Phone: 203-576-4737
Office: Tech Building Rm 225 (Rm 228)
website: http://kiwi.bridgeport.edu/CPE510
username: pwd:
GA: Mohamad Abuzneid
GA eMail: mohamad@bridgeport.edu
Grading
- Lectures & materials are all on the website.
- Phd students are grouped
- Masters students are grouped
- Assignments & Projects are KEY to getting a good grade.
- Prof: Mentioned about how students do copy each other, the test will really determine what you have really learned.
Computer Architecture A Quantitive Approace , 4th Edition
by.John L. Hennessy (Author), David A. Patterson (Author)
Authors are Inventors of Reduced Instruction Set Architecture - RISC
Authors are Inventors of Reduced Instruction Set Architecture - RISC
Course Approach
Goal of the course is to design a computer
I. A review ...
- A computer is a digital system
- Key ideas:
- registers
- flipflops
- adders
- counters
- sequential circuits
II. Then we will design a small computer:
Hands, legs, arms - DATAPATH
Brain - CONTROL
- With 8 or so instructions
- DATAPATH --> Parts or building blocks
- CONTROL --> The brain of the system
Hands, legs, arms - DATAPATH
Brain - CONTROL
A single goes to brain, to tell other parts what action to do.
A computer is built out of registers,
A computer is built out of registers,
which are a collection of flipflops, which store binary numbers,
we use buses to connect one register to others together, wires
sometimes we are connecting many together so we need ..
multiplexers, duplexers,adders & Multiplers
(ALU) Arithmatic & Logic Unit
sometimes we are connecting many together so we need ..
multiplexers, duplexers,adders & Multiplers
(ALU) Arithmatic & Logic Unit
A computer needs a brain (control) where to go and what to do, it is called a sequential circuit.
*** Once we know how a small computer works, then we will design a more involved computer.
Computers - speed is a critical design component
RISC - Reduced Instruction Set Computers, textbook authors are inventors
"Pipelining" RISC is heavily designed pipeline
we will design 32 bit processor.
We have multi-core CPU's in our computers today, inside one chip there are many CPU's
Computer is a CPU - connected to Memory via address bus, data bus, control bus
CPU itself is a data path interacting with some control.
2nd part of the course will be on
- multi processing, including multi core CPU's
- will also look at some research papers, on latest
***
We will be doing 1 Project, not yet finalized. read on a topic, come up with an idea, and try to improve on what you have read, with new idea.
***
Don't be shy, with even simple questions, keep asking questions.
?? So how do we have this dialogue, without Blackboard?
***
I. Review of Digital Design
I. Review of Digital Design
1. Combinational circuit:
- where output is a direct function of inputs, as the input changes the output changes
2. sequnetial circuit desing
- synronoize design
- Asyncronize design
Combinational Circuit Design Rules:
1. Identify inputs & outputs for the system
2. Draw a block diagram,
a. number of inputs
b. number of outputs
3. Create one k-map for each output,and size of k-map = to number of input variables
a. 3 inputs = 3 variable k-map
b. 4 inputs = 4 variable k-map
Example:
Design a circuit that can detect, an incoming 4-bit number is prime
Design a circuit that can detect, an incoming 4-bit number is prime
a -
b -
c - p = 1/0 true/false
d -
1 k-map with size = 4 variable k-map
p = AB + AD + BCD +BCD
***
Another example:
The number can only be from 0 to 9
p=AB+AD
********
Time Delay:
Delay of each gate =
What is the delay in your system, after how much do we need to see the output correctly?
Total delay = 3
Delay without an inverter = 2
*******************************************************************
Fundamental Theorem of Logic Design
"Any logic expression, no matter how complicated it is, can be expressed as a 2-level logic"
"Any logic expression, no matter how complicated it is, can be expressed as a 2-level logic"
*******************************************************************
?? is the delay the number of gates (or questions) or/nor
***
Let's design a more complicated circuit
Example: Design a fast 2-bit
Adder, that can add 2 2-bit numbers.
Adder, that can add 2 2-bit numbers.
we want it fast to achieve a delay of 2
inputs outputs
a1 -
a0 -
[ 2-bit adder ] -- c2
b1- -- c1
b0 - -- c0
how may k-maps do we need?
- we need 3 maps one for each output
- each kmap size will be a 4 variable kmap size
once you have the maps drawn, identify which kmap is for which output
?? Will I have to know how to add binary numbers in this class to get an A?
?? I don't know my prime numbers since grade school?
## As an exercise for home complete the 2-bit adder.
## How much delay will there be from the in put to the output? 2
It does NOT always come out 2
****
Example: Design a fast 3bit adder
Inputs [3 bit adder] outputs
a2 - = c3
a1 - = c2
a0 - =c1
b2 - =c0
b1 -
b0 -
The highest number we get with 3 bits =7
when we add 7 + 7 = 14
111 = 7
111 = 7
---------------
1110 = 14 so we need 4 outputs
so we need 4 k-maps one for each of the outputs
cells in a 4 variable k-map?
k-map = 2(power of 4 ) = 16 cells
cells in a 6 variable k-map?
k-map = 2(power of 6) = 64 cells
- Now it is getting complicated ... no it was complicated much earlier!
*******
Even Harder Problem: Design a 64bit adder.
Today's processors are capable of adding 2 64bit numbers together, at any given point in time.
how many outputs will we have? 65 outputs, when you add to 64 bit numbers, you will need one more output.
What would be the size of the k-map?
k-map = 2(power of 128) = 3.40282367 x 38 (power of 38)
*****
summary thought
when dealing with combinational logic
Is easy to design if the number of total inputs <= 6
-- One k-map per output
-- Size of k-map = number of inputs
This is not a real world, because you will need many inputs 64, 128, etc
?? How do we design if the number of inputs is >= 6
1) Apply some Heuristic Approach - don't try to solve the whole problem at once.
2) Use a BIT slice approach, - break it into a 1 bit problem
BIT SLICE APPROACH!
Rather than create a 64bit adder, create a 1 bit adder.
** we will design a 1 bit adder
** then by putting 64 1 bit adders together will create a 64bit adder,
** but this will cause a delay, at a 2 each
** the total delay will be 2 * 64 stages = 128 delay
** Not very efficient!
- because the problem is very complicated we can not reduce this to a 2 delay.
-
if the # of variables is > 6 we can cascade them together, it will be less logic, but it will come at a cost, of time delay.
HEURISTIC APPROACH:
Example: Design an b-bit priority encoder
Inputs Outputs
i0 --> = o0 = 0
~to~ = o1 =0
i7 --> = o2 = 1
Suppose i4 & i1 appear at the same time?
we want to recognize only 1
the output iOS a binary code for the input number that has the highest priority
if only i4 is input the above means, that input 4 has been recognized
if i4 & i6 is input -- suppose we want to give higher number, higher priority, in this case the system needs to recknoize the higher number and send it as output
if inputs are i2, i4, i7 what would be the outputs?
so i7 is the highest input channel coming in,
7 = 111 in binary
*
i2,i3,i4 = 4 is the highest = 100 in binary
Only the output for the highest number needs to be generated based on the rule for this priority encoder.
We have 8 inputs
We have 3 outputs
1 k-map per output, means 3 k-maps, each with a size of
k-map = 2(power of 8) = 8 variable k-map = nobody knows how to draw an 8 variable k-map
how about with 32 inputs
*So, using a heuristic encoder, it is easier, and you don't' need to use maps
Define Intermediate Outputs H0 - H7
that recognize a particular input:
e.g.
H0 = I0 (none of the others)
H1 = I1 (none of the others)
H2 = I2 (none of the others)
H3 = I3 (none of the others)
etc.
O0 = ho+h3+h5+h7
O1 = h2+h3+h6+h7
O2 = h4+ h5+h5+H6+H7
************************** END OF LECTURE 1 ********************
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